October 6, 2026 · Timothy O’Brien
Vaire Says It Can Build Near-Zero-Energy Chips. Is This Even Real?
Vaire's whitepaper reads like free-energy rhetoric, but the physics is real, the test silicon is real, and a commercial processor is still missing. The distinction matters for anyone planning capacity.
I started reading Vaire Computing’s whitepaper with roughly the reaction you’d expect to the phrase “Near-Zero Energy Computing.”
Come on.
If someone tells me they’ve invented a computer that barely uses energy and barely produces heat, my first assumption is that somewhere in the next five pages I’m going to encounter either a perpetual-motion machine or cryptocurrency.
But Vaire is weird, because this appears to be real. Not “they have a near-zero-energy replacement for an NVIDIA GPU” real. But the physics is real, the engineering approach is real, and they have actually fabricated silicon that demonstrates a piece of it.
The trick is to stop throwing the energy away
A conventional CMOS circuit repeatedly charges and discharges tiny capacitances as transistors switch. Almost all of the electricity a chip draws ends its life as heat; an old joke among engineers says a computer is a toaster that happens to perform calculations. Most of that heat comes from overwriting: when a circuit replaces the information it holds, the old energy has to go somewhere, and somewhere means heat.
Vaire is working on something called adiabatic reversible computing, and there are two ideas tangled together in that phrase. The first is logical reversibility. In normal computation, intermediate information gets discarded. Landauer’s principle, established at IBM in 1961, says erasing information carries a real thermodynamic cost, and today’s chips pay more than a thousand times that minimum, mostly by dumping each signal’s energy as heat. Reversible computation arranges operations so the previous state can be reconstructed rather than destroyed. The catch that stumped Landauer himself was memory: keep every intermediate result and you fill the machine with garbage. Charles Bennett showed the way out in 1973. Instead of storing the intermediates, run the computation backward once you’re done with them, and recover the energy on the way.
The second idea is more immediately practical: energy recovery. Instead of abruptly charging a transistor and then dumping that stored energy to ground, you change the voltage gradually (a trapezoidal waveform, not a square wave) and use resonant circuitry to capture the energy and feed it into the next operation. The power supply becomes part of the clock, something like a microscopic electrical flywheel moving energy into and back out of the logic instead of letting it escape. Think regenerative braking, except inside a chip.
That basic approach has decades of serious research behind it (MIT built reversible-logic test chips in the 1990s) and a known limitation: recovered energy leaked out through the external power supply, so wall-plug power barely improved. Vaire’s pitch is the missing piece, put the resonator on the chip, next to the logic, so the energy never has far to travel.
This is where Vaire’s whitepaper actually does the company a disservice. There are passages about pendulums and energy “cycling” that read perilously close to free-energy rhetoric. The company talks about chips that generate “negligible amounts of heat,” about eliminating the need for dedicated cooling, about efficiency “potentially orders of magnitude greater than conventional logic.” 8 Those are very large claims. But underneath them is legitimate semiconductor engineering, and the honest version of the pitch, more silicon area, lower frequencies, engineering discipline, is in the whitepaper too, if you read past the metaphors.
And they have a chip
This is the part that changed my opinion. In 2025, Vaire fabricated a 22-nanometer test chip called Ice River. EE Times reported an energy-recovery factor of 1.77 for a capacitor-array test structure and 1.41 for a shift register, meaning the resonator-driven circuit dissipated less power than the same structure driven conventionally. (The whitepaper defines the recovery factor this way: traditional logic is 1.0, so anything above 1 means the same energy drove more than one operation.) The test silicon included reversible logic, the energy-recovery resonator, its driver, and the unusual passive power-clock distribution network the system needs. Ice River ran at a data frequency of 500 MHz, and much of the design was done semi-manually because there is almost no design automation for this kind of circuit. 1 IEEE Spectrum put the same result in rounder numbers, roughly 50% energy recovery in the resonator circuit. 2 This is not a SPICE simulation. They sent a design to a semiconductor fab and got working silicon back.
MIT Technology Review profiled Vaire’s CTO Hannah Earley in September and reported that the company has raised more than $12 million. It quoted Igor Markov, a researcher in electronic design automation, on the state of things: “It’s clear they have something interesting,” he said, but the company will need “a series of increasingly realistic and convincing demonstrations to attract the industry support needed for commercialization.” 3 That feels like exactly the right assessment.
But they haven’t built the thing they’re selling us yet
Ice River is not a near-zero-energy processor. It is not an AI accelerator running inference at one-tenth the power of a GPU. And it certainly doesn’t establish that a data center can eliminate most of its cooling.
It is a proof that Vaire can recover energy from relatively small circuits fabricated in ordinary CMOS, and even there the numbers need careful boundaries. The “50%” figure Vaire announced applies to the resonator alone; the company acknowledged it excludes significant overheads elsewhere in a complete system. 7 Fortune reported the results had not yet been independently verified, though test kits were on their way to customers and academic labs. 4 Between a test structure and a product there is an enormous engineering distance: power-clock distribution, resonator integration, reversible logic families, area overhead, memory, interconnects, interfaces with conventional CMOS, and an EDA ecosystem that was never built to design this kind of chip.
Vaire’s own researchers say the same thing. A September 2025 AIP paper by Vaire senior scientist Michael Frank and Alexander Edwards of the Laboratory for Physical Sciences names exactly these as the open problems: resonator development, adiabatic reversible logic families, EDA tool support, and basic hardware algorithms and IP. 5 The paper argues there are no fundamental barriers, which is what you’d hope, and also exactly what you’d expect the authors to believe.
The academic record on adiabatic CMOS is considerably less breathless than Vaire’s materials. A 2021 analysis of several approaches concluded that, in the SoC scenarios it studied, roughly 3× power savings in PFAL was about the best achievable, a low return, in the authors’ words, given the required investments in area and complexity. 6 Vaire believes its on-chip resonator changes that equation dramatically. Maybe it does. Nobody outside the company has measured it yet. So I wouldn’t buy the “near-zero” part yet.
Here’s why I care anyway
The most interesting thing about Vaire isn’t the possibility of zero-energy computing. It’s capacity.
We’ve spent the last few years talking about AI electricity consumption as though it is primarily a cost problem. Increasingly it isn’t. It’s a capacity constraint. A data center only has so many megawatts available. A rack can dissipate only so much heat. A facility can deliver only so much power. Cooling, substations, generators, transformers and grid interconnects are becoming constraints on how much computation can physically exist in a particular place.
That changes the economics. If Vaire eventually makes a chip that performs the same useful work with half the power, it hasn’t merely reduced the electric bill; it has potentially doubled the amount of compute that fits inside the existing power envelope. Reducing heat also changes density, packaging and eventually 3D integration, because a chip that stays cool can stack.
That’s why Vaire doesn’t need to achieve “near-zero energy” for this to matter. A practical accelerator with competitive performance and a 2× or 3× improvement in useful computation per watt is interesting. At 10×, the architecture of data centers starts changing. At 100×, we’re talking about an entirely different computing industry.
And if it really can eventually get into the orders-of-magnitude territory Vaire talks about? Then we’ve been solving the wrong problem. We’ve been trying to build enough power infrastructure to feed computation. Vaire is asking whether computation needs to consume all that power in the first place.
So: is Vaire real?
Yes. Reversible computing is real. Adiabatic energy recovery is real. Vaire is a real semiconductor company with real researchers and real fabricated silicon demonstrating net energy recovery. But near-zero-energy AI computing is not real yet. There’s still an enormous leap from recovering energy inside a test structure to winning on performance, area, reliability and total system power against some of the most aggressively optimized silicon ever built.
That’s what makes Vaire interesting. It isn’t a perpetual-motion machine. It also isn’t a product yet.
For me, the number to watch isn’t Vaire’s resonator efficiency. It’s something much more boring: useful compute per megawatt. If they can move that number materially, nobody will care whether they ever actually get to zero.
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Sources
1. Sally Ward-Foxton, EE Times, September 3, 2025: Vaire Demos Energy Recovery With Reversible Computing Test Chip — energy-recovery factors 1.77 (capacitor array) and 1.41 (shift register; a 9/4/25 correction moved the 1.41 from an adder to the shift register), 500 MHz data frequency, semi-manual design, the passive power-clock distribution network, and the company’s roadmap commentary. Article corrected September 4, 2025.
2. Dina Genkina, IEEE Spectrum, January 2, 2025, updated May 22, 2025: Reversible Computing Escapes the Lab in 2025 — the 50%-of-energy-recovered-in-the-resonator framing, the MIT 1990s demos and their external-power-supply limitation, Frank’s Sandia work, the MEMS resonator path, and the 4,000× long-run roadmap claim.
3. September 8, 2026: This start-up founder is teaching chips how to recycle (their energy) — MIT Technology Review — Earley’s resonator design, the company’s founding in 2021, more than $12 million raised, and Igor Markov’s “increasingly realistic and convincing demonstrations” assessment.
4. Jeremy Kahn, Fortune, May 20, 2025: A startup working on ‘reversible computing’ chip for AI says initial tests show a 50% energy savings — “yet to be independently verified,” test kits en route to customers and academic labs, the trapezoidal-resonator engineering challenge, and the GPU/parallelism positioning.
5. Michael P. Frank and Alexander J. Edwards, “Industry perspective: Limits of energy efficiency for conventional CMOS and the need for adiabatic reversible computing,” APL Electronic Devices 1(3), September 29, 2025. doi:10.1063/5.0279617 — the open-problems list (resonator development, logic families, EDA tooling, hardware algorithms/IP) and the no-fundamental-barriers argument. Frank is a Vaire senior scientist; Edwards is with the Laboratory for Physical Sciences.
6. K.S. Rengarajan, S. Mondal and R. Kapre, “Challenges to adopting adiabatic circuits for systems-on-a-chip,” IET Circuits, Devices & Systems 15(6), 2021. doi:10.1049/cds2.12053 — the 3× power savings conclusion for PFAL in the studied SoC context, described by the authors as a low return given area and complexity costs.
7. Charlotte Trueman, Data Center Dynamics, May 22, 2025: Vaire Computing tapes out demo chip capable of recycling 50% of its energy-intensity — the 50% average recovery figure and the company’s note that it applies to the resonator and excludes significant additional energy overheads.
8. Vaire Computing, The Technology of Near-Zero Energy Computing (whitepaper, accessed October 6, 2026) — the pendulum/energy-cycle framing, the “negligible heat” and “eliminates dedicated cooling” claims, the recovery-factor definition, and the stated trade-offs (more silicon area, lower frequencies).
