Exotic Hardware: Quantum and Emerging Capacity

How to read this chapter

The chapter separates research progress from usable capacity: why most of this hardware stays out of next year’s plan, what evidence would bring it in, and which work cannot wait.

1. What counts as exotic — unproven for our workload.
2. Quantum, honestly assessed — results, estimates and roadmaps.
3. What cloud quantum services sell — simulators, hardware access and experiment budgets.
4. Post-quantum cryptography is a different project — the work with deadlines.
5. When specialist hardware becomes a real procurement — owners, stopping rules and lasting obligations.
6. Rare is not exotic — RISC-V, DPUs, CXL and Arm.
7. The evidence standard for emerging architectures — five conditions, nine families.
8. The watch list — what would change a decision, and who will notice.
9. Where to look next — sources and open-source tools.
10. Two or three beats ahead — the answer for next time.

What counts as exotic

Here, exotic hardware means a computing architecture whose usefulness for our workload has not yet been established, not everything new or scarce. A GPU that is difficult to obtain is still familiar production capacity, and a commercially available specialist system can deserve a place in the plan without becoming a standard enterprise platform.

Power and cooling are a related question with different specialists. I do not want a placement review to disappear into an hour of speculation about nuclear reactors, or to dismiss a power constraint because another team owns it; the plan needs the facility team’s actual supply, cooling and readiness commitments.

The boundary of a claim matters as much as its size. Over a 54-day snapshot of Meta’s Llama 3 pre-training on up to 16K H100 GPUs, the job stopped 419 times unexpectedly, about once every three hours, and Meta still reported more than 90 percent effective training time.¹ Chapter 10 drew the lesson for familiar accelerators: the cost that matters belongs to the complete system, recovery included. Every claim in this chapter gets the same treatment.

Quantum, honestly assessed

Microsoft’s open-source Quantum resource estimator lets a specialist examine that dependency: given a quantum program, a hardware model, an error-correction scheme and an error budget, it reports the physical qubits and runtime required, trading one for the other.⁷ I would ask for several plausible hardware assumptions and which of them move the result most. The output makes a research requirement inspectable; it does not show that the modeled hardware exists or will arrive.

Cryptanalysis makes the distinction consequential. Craig Gidney’s 2025 estimate puts factoring a 2,048-bit RSA integer at fewer than a million noisy qubits running for less than a week; his 2019 estimate with Martin Ekerå, under the same hardware assumptions, needed about twenty million qubits for eight hours.⁸ Better algorithms and error-correction engineering cut the requirement twentyfold, trading qubits for time, and nobody has built either machine. Numbers that move that far on paper are a reason to prepare now rather than to forecast the year the risk arrives.

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What cloud quantum services sell

A quantum-service catalog sells classical computing too. Amazon Braket lists state-vector, density-matrix and tensor-network simulators alongside access to quantum processing units, or QPUs.⁹ Simulation is legitimate development work that belongs in the classical capacity forecast.

Real QPU access is charged by device, by task, by repeated circuit execution, called a shot, and by reserved time.¹⁰ A shot on one device is not necessarily comparable with a shot on another, because the circuit, error behavior and repetitions needed for a useful estimate differ.

On Azure Quantum each provider sets its own pricing, from charges per circuit operation and shot to charges for execution time, with Azure infrastructure billed separately.¹¹ The experiment record should therefore name the provider, target, pricing plan and circuit rather than report only “quantum usage.”

It is possible to estimate an experiment’s cost without claiming that quantum computing has a universal unit price. Take rates of $0.30 per task and $0.01 per shot. One task with 2,000 shots costs $0.30 + 2,000 × $0.01 = $20.30, excluding classical preparation, retries and any other charges. As it happens, those figures match a live quote on one service: Amazon Braket publishes a $0.30 per-task charge on every QPU it lists and a $0.01 per-shot price for its QuEra Aquila device, while other devices on the same service range from $0.000425 to $0.08 per shot.¹² The planning question is how many such tasks the research program expects to run and what would justify the next round. An experiment budget can be precise about its spending limit while remaining uncertain about its scientific result.

Post-quantum cryptography is a different project

One reason to begin before a cryptographically relevant quantum computer exists is the possibility of collecting encrypted traffic now and decrypting it later. The significance depends on how long the information must remain confidential and how long migration will take. NIST’s migration guidance starts with discovering cryptographic dependencies, evaluating risk and working with suppliers.¹⁴ Security should establish the applicable requirements and deadlines. In the United States, an executive order signed June 22, 2026 set dates of exactly that kind: federal high-value assets and high-impact systems must use post-quantum key establishment by December 31, 2030 and post-quantum digital signatures by December 31, 2031, and the order directs procurement rules extending similar requirements to federal contractors.¹⁵ A government-system timetable is not automatically a universal deadline for every private application. But a deadline that reaches suppliers through federal purchasing reaches further than the agencies it names. NIST’s own transition report, NIST IR 8547, published in final form in October 2026, sets the timetable for the standards behind such deadlines: quantum-vulnerable public-key algorithms with a 112-bit security strength are deprecated after 2030 and disallowed after 2035.¹⁶

The capacity team belongs in the migration because a protocol change can affect connection size, CPU use, memory and compatibility. The sizes change a lot: an ML-KEM-768 encapsulation key is 1,184 bytes and its ciphertext 1,088, against 32 bytes for an X25519 key share, and an ML-DSA-65 signature is 3,309 bytes.¹⁷ A TLS ClientHello carrying a post-quantum key share no longer fits in one packet, and when browsers began sending one, some servers and network appliances rejected the connection.¹⁸ Larger messages do not make every operation slower; algorithm, implementation, hardware and handshake design all matter.¹⁹ Test the selected stack at representative connection rates, including failed negotiations and fallback, before putting a fixed percentage overhead into the forecast.

Stored data needs a separate inventory. Quantum-vulnerable public-key mechanisms and symmetric bulk encryption are different dependencies; a quantum threat does not imply that every archive encrypted with AES must be decrypted and encrypted again.²⁰ Some data may need only its key protection or key establishment changed. If bulk re-encryption is necessary, identify the affected volume, effective processing rate, deadline and overlap space. Only then is there a batch-capacity requirement to size.

Security owns the migration and its requirements; capacity sizes the resources and timing, and neither waits for anything on the hardware watch list.

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When specialist hardware becomes a real procurement

A research group can supply a legitimate requirement for quantum, neuromorphic or another specialist system, and it deserves evaluation under the ordinary rules: name the work, budget, access conditions, owner and stopping rule. Uncertain demand does not make attribution or contractual obligations disappear.

For cloud access, establish where the data and computation may reside, which device is required, what access windows are available and how much classical support the experiment needs. Research demand follows an experimental calendar rather than customer traffic, and a failed experiment can be scientifically useful, so count completed experiments and business results separately.

Buying the service remains the better default. A physical system brings facilities and staffing requirements that depend on its architecture: a superconducting quantum system has different cooling and control needs from a trapped-ion or photonic design, and a supplier’s scientists do not become the customer’s operating team. Price installation, maintenance, specialist coverage and replacement, and say who will operate the equipment after the project team has moved on; a small research budget can commit the organization to years of maintenance contracts, specialist salaries and floor space.

Rare is not exotic

A capacity team also needs to recognize hardware that is unfamiliar to a workload owner but already purchasable.

RISC-V is an open instruction-set architecture, a specification implementers can build processors from.²¹ An open specification does not make chip design, software support or manufacturing free; the question is whether a supported product runs our application and what moving to it changes.

DPUs and smart NICs move some networking, storage and security processing off the main CPU, as AWS’s Nitro System does.²² The instance’s network and storage limits still bound what the offload delivers, so measure the complete instance.

CXL, Compute Express Link, provides coherent connections among processors, accelerators and memory devices, and its specifications support memory expansion and, in suitable systems, pooling.²³ Those are different capabilities, so establish the topology, allocation behavior, bandwidth and latency of the implementation being purchased.

A move to Arm instances such as AWS Graviton or Azure Cobalt is an application decision as well as a scheduling one.²⁴ Microsoft’s documentation gives each Cobalt 100 vCPU a full physical core, a reminder to check what the purchasing unit represents before comparing core counts.²⁵ Software compatibility, licenses and measured performance decide the move; a catalog offering makes the experiment practical without settling the migration cost.

None of these needs an exotic watch list; where they support our work, they belong in ordinary procurement.

The evidence standard for emerging architectures

Most of the hardware in this section will not appear in next year’s capacity plan, and the reason should be specific. An architecture enters the plan when there is evidence of all five of these for a workload we run:

1. Quality: results that meet the workload’s accuracy, latency or answer-quality requirement.
2. Boundary: a figure that says whether it covers one operation, a chip, a card or the complete system.
3. Comparison: a current measurement against the best conventional alternative, which keeps improving.
4. Supply: a price, a delivery date, supported software and a repair process.
5. Obligations: supplier concentration, contract terms and an affordable exit.

Research systems rarely pass the first condition for our workloads. A product that passes all five is ordinary procurement. Everything in between goes on the watch list with its missing condition named.

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Neuromorphic

Neuromorphic designs borrow two ideas from nervous systems. The hardware is event-driven, so a core stays idle until an input changes and energy tracks activity rather than a clock; and the computation is often a spiking neural network, in which values travel as pulses whose timing carries information. Those properties suit always-on sensing, such as a wake word, motion in a camera feed or vibration in a machine, far better than bulk training or high-throughput inference.

The largest systems are research systems. Intel’s Hala Point combines 1,152 Loihi 2 processors and supports roughly 1.15 billion artificial neurons at a stated maximum of 2,600 watts.²⁶ Manchester’s SpiNNaker machine connects over one million ARM cores to model spiking networks in biological real time. Its successor chip, SpiNNaker2, runs in TU Dresden’s 35,000-chip SpiNNcloud machine, and a university spin-off of the same name sells SpiNNaker2 systems with a claimed eighteenfold energy-efficiency advantage over GPUs.²⁷ The research figures describe simulation capacity, and the GPU comparison is a vendor claim to test against the standard above.

The commercial products are small and shipped: BrainChip’s Akida processor, sold as chips and licensed IP;²⁸ SynSense’s Speck, an event-based image sensor and spiking processor on one chip;²⁹ Innatera’s Pulsar spiking microcontroller;³⁰ and Prophesee’s event-based vision sensors, which report a pixel only when its brightness changes.³¹ They are component decisions for the teams that design devices.

A neuromorphic chip can spend milliwatts where a general accelerator would spend watts, and for sparse, event-driven sensing that comparison is real. It weakens when data must be converted, when models retrain often, or when the surrounding system draws most of the power. Neuromorphic hardware stays out of a data-center plan until someone shows an end-to-end comparison, at the required accuracy, on a workload we run there.

Photonic

Optical interconnect and optical computation are different products, and the market offers much more of the first.

An optical interconnect replaces a copper link with light, which carries more bandwidth farther at lower energy per bit as signaling rates climb. Lightmatter’s Passage products link processors optically;³² Ayar Labs puts its TeraPHY optical chiplet in the processor’s package;³³ Celestial AI’s Photonic Fabric, now part of Marvell, links processors and memory;³⁴ Lightelligence’s Photowave links serve PCIe and CXL memory expansion;³⁵ and Salience Labs and Black Semiconductor are developing photonic switching and chip-to-chip links.³⁶ Volantis, a funded newcomer, is developing chip-to-memory optical links built on micro-VCSEL lasers and plans its first integrated inference engines for 2027.³⁷ Manufacturing capacity for the family is forming too: in October 2026 a Japanese government program selected a four-company group led by NTT Innovative Devices, with NTT advising, to develop mass-production technologies for optical chiplets that connect processors with light, targeting more than a tenfold increase in manufacturing productivity over research-stage processes.³⁸ In all of them the arithmetic stays electronic; the light moves the data. Interconnect usually arrives inside a supplier’s system and is judged with it: bandwidth, latency, energy per bit against the link replaced, laser and connector reliability, and what a repair looks like.

Optical computation is a smaller, earlier field that performs parts of a calculation, especially linear algebra, with optical operations.³⁹ Q.ANT, a 2018 spin-off from the German industrial firm TRUMPF, offers a PCIe photonic co-processor; its second generation entered evaluation at the Leibniz Supercomputing Centre in March 2026, with published gains measured against Q.ANT’s first generation, not against GPUs.⁴⁰ Lightmatter’s 2025 Nature paper shows why the boundary matters. Counting only the energy to encode data into its photonic tensor core, the authors report 262 trillion operations per second per watt; the complete processor averaged 0.81 (1.75 at peak clock), in the range of the GPUs in their comparison table.⁴¹ A buyer installs the second number, which is more than 300 times lower. Until a supplier can show the complete system, with its inputs, control, detection and conversion, on a workload we run, optical computation stays on the watch list.

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Analog compute-in-memory

Analog compute-in-memory represents values through physical properties such as conductance and uses the circuit’s behavior to perform arithmetic. Mythic describes an implementation using analog operations in flash-memory arrays.⁴² Such designs seek to reduce data movement, but converters, control and calibration remain part of the system.

Digital floating-point arithmetic is not infinitely exact either, so the comparison needs an accuracy requirement that both must meet. Ask how precision, variation, temperature and model updates affect the deployed result, then compare useful throughput, power, cost and support under those conditions.

Resistive memory as compute

Resistive random-access memory, or ReRAM, belongs to the memristor family: it stores bits as resistance in an oxide cell, and foundries and chipmakers now license it as embedded non-volatile memory where flash is hard to scale. Weebit Nano reports JEDEC-based qualification in DB HiTek’s 130-nanometer process and three customer designs taped out by mid-2026, each facing what it says can be 12 to 18 months of qualification before mass production; its ReRAM has also been fully qualified in SkyWater’s 130-nanometer process, a United States foundry, since 2023.⁴³ Embedded ReRAM is therefore component sourcing with a long lead time, not a watch-list entry. The exotic version uses an array of resistive cells for analog arithmetic in place: compute-in-memory on a different substrate, with the same questions about precision, variation and converters. Ask which of the two a supplier is selling. Weebit now offers both: the Matrix research program it launched in November 2026 provides qualified researchers a development kit built around a 32-by-32 resistive crossbar array for compute-in-memory experiments, alongside the embedded ReRAM it licenses for production.⁴⁴

Memory and packaging

Memory capacity and bandwidth already constrain accelerator configurations, as Chapter 10’s calculations showed. New memory connections or packaging can change what fits and how quickly data reaches the processors, and can add placement, repair and supply constraints. Those are experiments for the hardware specialists, measured on the configuration we can buy, and the answers reach the plan through the next pool’s configuration.

Thermodynamic and probabilistic computing

Thermodynamic computing uses physical noise as a resource instead of spending energy to suppress it. Diffusion models, Bayesian inference and simulated annealing consume random samples in enormous numbers, which conventional hardware generates with pseudorandom algorithms; a thermodynamic chip lets a circuit fluctuate and reads samples from it. Normal Computing announced the tape-out of CN101, which it calls the first thermodynamic computing chip, in August 2025, with successors on its roadmap for 2026 and for late 2027 or early 2028.⁴⁵ Extropic signed a non-binding letter of intent in July 2026 for up to $75 million in U.S. Department of Commerce research funding for its thermodynamic sampling units.⁴⁶ Extropic’s hardware page lists a silicon prototype from early 2025 and a research platform from later that year, with a stick and a PCIe card carrying, by the company’s count, millions of probabilistic bits advertised for early access in 2027.⁴⁷ A tape-out, a roadmap, a letter of intent and early-access hardware are not measured results on a workload. Extropic itself places much of the remaining work “beyond the chip itself, in the systems around it,” which is where the boundary condition applies.

Reversible computing

Most logic gates discard information: an AND gate’s output does not reveal its inputs. Landauer showed that erasing a bit has a minimum energy cost, and today’s chips spend more than a thousand times that minimum, mostly by dumping each signal’s energy as heat when it switches.⁴⁸ Reversible designs keep enough information to undo a computation, ramp voltages gradually, and return signal energy to a resonator for reuse. Vaire Computing’s 22-nanometer Ice River test chip showed the mechanism working in 2025: driven by its resonator, a shift register dissipated 1 ÷ 1.41, or about 71 percent, of the energy of the same circuit driven conventionally, and a capacitor array about 56 percent.⁴⁹ That is a measured result, more than most watch-list entries can show, but on test structures, with no workload and nothing to buy. Watch for a processor running a named workload with its resonator losses counted.

Quantum annealing

Quantum annealing is a shipped, priced product that solves a different problem from the gate-model machines above: instead of running general circuits, an annealer searches for low-energy states of an optimization problem encoded in its hardware. D-Wave sells access through its Leap cloud service and has offered service-level agreements to production customers since 2024, citing its own monitoring of more than 99.9 percent availability. AWS Marketplace lists a twelve-month Leap subscription at $70,000, non-cancellable and non-refundable.⁵⁰ That is a commitment on ordinary commercial terms, and it gets the ordinary questions: which of our optimization problems encode well, how good the answers must be, how the hybrid solver’s classical work is billed, and what a good classical solver achieves on the same instances for the same money. In October 2026, D-Wave, which had built its business on annealing, opened a beta program for a gate-model quantum computing simulator on the same Leap service, with BBVA, Florida Atlantic University and the Jülich Supercomputing Centre among the early users.⁵¹ The simulator is classical software; the dual-rail gate-model hardware it prepares customers for is on the roadmap, with a Nature-published two-qubit entangling gate as the experimental evidence so far. The supply base is consolidating too. In October 2026, D-Wave extended its manufacturing agreement with SkyWater, the Minnesota foundry that has fabricated its processors for more than a decade — a foundry now owned by IonQ, a competing quantum vendor whose acquisitions this year also include a photonics manufacturer and a cybersecurity company.⁵² Both companies describe the collaboration as continuing. The obligations condition in this chapter asks about supplier concentration; here it reaches one level deeper, because the fabrication of the device you can rent now sits inside another supplier’s acquisition strategy.

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Wafer-scale

Wafer-scale processors keep a much larger connected area of silicon than a conventional die. Ordinary manufacturing exposes a limited field at a time; one common full-field lithography specification is 26 by 33 millimeters.⁵³ Wafer-scale designs connect across field boundaries and tolerate defects, so one field no longer limits the processor.

The idea has a history worth knowing before the first vendor meeting. In 1980 Gene Amdahl, already famous for the IBM-compatible mainframes that carried his name, founded Trilogy Systems to build a mainframe from wafer-sized chips, and it became the best-funded startup Silicon Valley had seen. In Amdahl’s later account, leakage between wiring layers kept yields low, each mask revision took eight months, and the three still needed would have used up almost all the money; Trilogy abandoned the design and in 1985 spent what remained buying another computer company. He added that the product would not have lasted anyway, because CMOS was coming.⁵⁴ That is the comparison condition at work: the new approach ran out of time while the conventional alternative kept improving.

Cerebras took a different route. Its Wafer-Scale Engine — the third generation carries 4 trillion transistors and 900,000 cores — replicates many small cores and routes around manufacturing defects, so a flaw costs a core rather than the wafer.⁵⁵ The company sells systems and inference services. The product has kept moving: in August 2026 the company introduced the CS-4, a rack-scale system built from three Wafer-Scale Engine 3 Turbo processors, which it claims delivers up to twice the CS-3’s speed and up to ten times its throughput per watt.⁵⁶ The demand side now has a named anchor: in January 2026, OpenAI announced a multi-year agreement to deploy up to 750 megawatts of Cerebras systems in tranches through 2028, and Cerebras has since powered an Ultrafast service tier for one of OpenAI’s models, initially in limited preview.⁵⁷

Cerebras’s own materials describe external memory expansion and multi-system clusters for large models,⁵⁸ so establish how the model is placed — on one wafer, across several systems or with external weight storage — before accepting the single-device framing. The CS-3 cluster datasheet specifies each node as a full 42U rack weighing 800 kilograms, with 34 kilowatts of provisioned power and either facility water or liquid-to-air cooling, so Chapter 10’s facility discussion applies unchanged.⁵⁹ And because one company supplies the architecture, the purchase carries single-supplier risk.

Wafer-scale systems can be bought today, which puts them nearer ordinary procurement than most of this section. Compare a quoted system or service with the alternatives on the actual workload, including latency, accepted throughput, availability, software support and supplier concentration. A second vendor would help negotiations but is not a precondition for useful capacity.

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The watch list

Match the effort to the organization’s exposure: one qualified reviewer with a short list may be enough for a smaller company, while a large research or infrastructure portfolio may justify a specialist team. Enter a supplier’s roadmap date as a claim, with the date the claim was made, and look again when that date arrives; a roadmap date copied into a plan is a commitment nobody approved. Bring a finding into the monthly review when it changes an assumption, opens an option or threatens an existing commitment.

Where to look next

This list gathers the organizations the chapter names, with open-source tools for experimenting before anyone buys hardware. Every link is the organization’s own account of itself, which is the kind of evidence this chapter examines rather than a substitute for examining it. Links checked November 9, 2026.⁶⁰

Quantum services

• Amazon Braket: simulators and QPU access from several providers.
• Azure Quantum: providers with their own pricing plans.
• IBM Quantum: hardware and the roadmap to Starling.
• Quantinuum: trapped-ion systems, available directly and through Azure Quantum.

Open-source projects

• Qiskit: IBM’s quantum development kit and simulators.
• Cirq: Google’s Python framework for quantum circuits.
• PennyLane: Xanadu’s hybrid quantum-classical library.
• Strawberry Fields: Xanadu’s photonic quantum library.
• Quantum Development Kit (Q#): Microsoft’s toolchain, including the resource estimator.
• Lava: Intel’s neuromorphic framework.

Post-quantum cryptography

• NIST Post-Quantum Cryptography project: the ML-KEM, ML-DSA and SLH-DSA standards and migration guidance.
• Open Quantum Safe project: the liboqs library and other prototypes, for testing rather than production.

Research neuromorphic systems

• Intel Hala Point and Loihi 2: the 1.15-billion-neuron research system.
• SpiNNaker at Manchester: the million-core platform, with the open-source sPyNNaker toolchain.
• SpiNNcloud: the TU Dresden spin-off selling SpiNNaker2 systems.

Commercial neuromorphic products

• BrainChip: the Akida processor, as chips and licensed IP.
• SynSense: the Speck sensor-and-processor chip.
• Innatera: the Pulsar neuromorphic microcontroller.
• Prophesee: Metavision event-based sensors.

Photonic interconnect and computing

• Lightmatter: Passage photonic interconnect.
• Ayar Labs: in-package optical I/O chiplets and light sources.
• Celestial AI: the Photonic Fabric, now part of Marvell.
• Lightelligence: Photowave optical links and optical-computing boards.
• Q.ANT: photonic co-processors.
• Salience Labs: photonic optical circuit switches.
• Black Semiconductor: graphene-based photonic chip-to-chip links.
• Volantis: chip-to-memory photonic interconnect for AI inference systems.
• NTT Innovative Devices: optical chiplet manufacturing and photonics-electronics convergence devices.

Thermodynamic, reversible and annealing hardware

• Normal Computing: the CN101 thermodynamic chip.
• Extropic: thermodynamic sampling units.
• Vaire Computing: reversible computing test chips.
• D-Wave: quantum annealing systems and the Leap cloud service.

Other emerging hardware and interconnect

• Mythic: analog compute-in-memory in flash arrays.
• Weebit Nano: embedded ReRAM for foundries and chipmakers.
• Cerebras: wafer-scale processors and an inference service.
• RISC-V International: the open instruction-set specification.
• Compute Express Link Consortium: coherent-interconnect specifications.

Two or three beats ahead

I want a capacity team to be two or three beats ahead: early enough to investigate a relevant change before a deadline turns it into an emergency. That is a working ambition, not a promise to predict which technology wins.

The next executive question should have a concrete answer. Here is the work already under way; here is the specialist following the remaining uncertainty; here is the result that would justify a purchase. If a supplier now meets that condition, we begin the comparison. If it does not, we can explain why the roadmap has not become a commitment.

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Notes and sources

1. Aaron Grattafiori and colleagues, “The Llama 3 Herd of Models,” 2024, https://arxiv.org/abs/2407.21783, section 3.3: a 54-day snapshot with 466 job interruptions, 419 of them unexpected, and more than 90 percent effective training time, on up to 16K H100 GPUs. One run, not a component failure rate; Chapter 10 discusses the figures and their limits.↩︎

2. Google Quantum AI and collaborators, “Quantum error correction below the surface code threshold,” Nature, 2024, https://www.nature.com/articles/s41586-024-08449-y. Accessible author account: https://blog.google/innovation-and-ai/technology/research/google-willow-quantum-chip/. The result concerns the demonstrated error-correction experiment, not enterprise workload economics.↩︎

3. IBM, “How IBM will build the world’s first large-scale, fault-tolerant quantum computer,” June 10, 2025, https://www.ibm.com/quantum/blog/large-scale-ftqc. Supplier roadmap and explanation of logical versus physical qubits; dates and delivered capabilities must be checked when procuring.↩︎

4. Google Quantum AI, “Bringing the magic: Google breaks open a bottleneck in quantum computing,” October 15, 2026, https://blog.google/innovation-and-ai/models-and-research/quantum-computing/magic-state-cultivation-quantum-computing/; the paper, “Magic state cultivation on a superconducting quantum processor,” is in Science, https://www.science.org/doi/10.1126/science.aee7961. First hardware demonstration of the technique: about a fortyfold error reduction and a reported 99.99 percent T-state logical fidelity on the Willow processor. The post notes estimates that up to 95 percent of a machine’s capacity can go to producing magic states and states that demonstration at larger scale remains. A vendor’s account of its own result.↩︎

5. Quantinuum, “Quantinuum Breaks Error-Correction World Record by 10x, Validating its Leading Path to Fault-Tolerant Quantum Computing by 2029,” October 19, 2026, https://www.quantinuum.com/press-releases/quantinuum-breaks-error-correction-world-record-by-10x-validating-its-leading-path-to-fault-tolerant-quantum-computing-by-2029. Vendor announcement: a 99.9995 percent logical fidelity on the commercial Helios system using a color code, ten times the company’s own September 2026 result on the same hardware; the announcement states its Helix code used 10 physical qubits per logical qubit against up to 37 for the color code, and links the result to its planned Apollo system. Quantinuum appears among Azure Quantum’s priced providers; the record and the roadmap claims are the company’s own.↩︎

6. IBM, “How IBM will build the world’s first large-scale, fault-tolerant quantum computer,” June 10, 2025, https://www.ibm.com/quantum/blog/large-scale-ftqc. Supplier roadmap and explanation of logical versus physical qubits; dates and delivered capabilities must be checked when procuring.↩︎

7. Microsoft, “Introduction to the resource estimator,” https://learn.microsoft.com/en-us/azure/quantum/overview-resources-estimator, and “How to install and use the Microsoft Quantum resource estimator,” https://learn.microsoft.com/en-us/azure/quantum/quickstart-microsoft-resources-estimator, checked October 3, 2026. Open-source resource modeling under stated application, hardware and error-correction assumptions, reporting a qubit–runtime frontier; no Azure account is required. No resource-estimator run is claimed here.↩︎

8. Craig Gidney, “How to factor 2048 bit RSA integers with less than a million noisy qubits,” 2025, https://arxiv.org/abs/2505.15917; Craig Gidney and Martin Ekerå, “How to factor 2048 bit RSA integers in 8 hours using 20 million noisy qubits,” 2019, Quantum 5, 433, 2021, https://arxiv.org/abs/1905.09749. Both assume a nearest-neighbor square grid, a 0.1 percent gate error rate, a one-microsecond surface-code cycle and a ten-microsecond reaction time. Resource estimates, not completed attacks or a delivery forecast.↩︎

9. Amazon Web Services, Amazon Braket pricing, https://aws.amazon.com/braket/pricing/, checked November 9, 2026. Simulator and QPU charging structures. On the checked date the published per-task fee was $0.30 on all listed QPUs — now including devices from AQT and IQM alongside Rigetti, IonQ and QuEra — and per-shot prices ranged from $0.000425 (Rigetti Cepheus) to $0.08 (IonQ Forte), with QuEra’s Aquila at $0.01 — the pair used in the text’s calculation. Prices are the provider’s published list at a point in time and must be re-checked when budgeting an experiment.↩︎

10. Amazon Web Services, Amazon Braket pricing, https://aws.amazon.com/braket/pricing/, checked November 9, 2026. Simulator and QPU charging structures. On the checked date the published per-task fee was $0.30 on all listed QPUs — now including devices from AQT and IQM alongside Rigetti, IonQ and QuEra — and per-shot prices ranged from $0.000425 (Rigetti Cepheus) to $0.08 (IonQ Forte), with QuEra’s Aquila at $0.01 — the pair used in the text’s calculation. Prices are the provider’s published list at a point in time and must be re-checked when budgeting an experiment.↩︎

11. Microsoft, “Pricing plans for Azure Quantum providers,” https://learn.microsoft.com/en-us/azure/quantum/pricing, checked November 9, 2026. Provider-specific operation/shot and execution-time charging, plus infrastructure charges. Confirm the current plan in the workspace before funding an experiment; no common rate or performance equivalence is inferred.↩︎

12. Amazon Web Services, Amazon Braket pricing, https://aws.amazon.com/braket/pricing/, checked November 9, 2026. Simulator and QPU charging structures. On the checked date the published per-task fee was $0.30 on all listed QPUs — now including devices from AQT and IQM alongside Rigetti, IonQ and QuEra — and per-shot prices ranged from $0.000425 (Rigetti Cepheus) to $0.08 (IonQ Forte), with QuEra’s Aquila at $0.01 — the pair used in the text’s calculation. Prices are the provider’s published list at a point in time and must be re-checked when budgeting an experiment.↩︎

13. NIST, FIPS 203, https://csrc.nist.gov/pubs/fips/203/final; FIPS 204, https://csrc.nist.gov/pubs/fips/204/final; FIPS 205, https://csrc.nist.gov/pubs/fips/205/final. Finalized August 13, 2024; key encapsulation and signature standards for classical implementation.↩︎

14. NIST NCCoE, “Frequently Asked Questions about Post-Quantum Cryptography,” updated June 30, 2026, https://pages.nist.gov/nccoe-migration-post-quantum-cryptography/FAQ/index.html. Inventory, migration, interoperability and benchmarking; applicable requirements depend on the organization and systems.↩︎

15. Executive Order 14412, “Securing the Nation Against Advanced Cryptographic Attacks,” June 22, 2026, published at 91 FR 38483, https://www.federalregister.gov/documents/2026/06/25/2026-12909/securing-the-nation-against-advanced-cryptographic-attacks. Sets federal transition deadlines for high-value assets and high-impact systems and directs rulemaking on contractor requirements. Implementation details and any successor guidance should be re-verified at each revision.↩︎

16. NIST, IR 8547, “Transition to Post-Quantum Cryptography Standards,” final October 27, 2026, https://csrc.nist.gov/pubs/ir/8547/final. Sets transition timelines for quantum-vulnerable algorithms — 112-bit-strength public-key algorithms deprecated after 2030, disallowed after 2035 — and supports implementation of Executive Order 14412 and OMB Memorandum M-26-15. Migration guidance for standards and their use, not a deadline for any particular system.↩︎

17. NIST, FIPS 203, Table 3, https://csrc.nist.gov/pubs/fips/203/final, and FIPS 204, Table 2, https://csrc.nist.gov/pubs/fips/204/final, for the ML-KEM-768 and ML-DSA-65 sizes; IETF, RFC 7748, 2016, https://www.rfc-editor.org/rfc/rfc7748, for 32-byte X25519 values. Hybrid deployments carry both.↩︎

18. “tldr.fail,” https://tldr.fail/, checked October 3, 2026. Servers and middleboxes that rejected ClientHello messages spanning more than one packet once browsers offered post-quantum key exchange, with patch status (table updated April 4, 2025).↩︎

19. NIST NCCoE, “Frequently Asked Questions about Post-Quantum Cryptography,” updated June 30, 2026, https://pages.nist.gov/nccoe-migration-post-quantum-cryptography/FAQ/index.html. Inventory, migration, interoperability and benchmarking; applicable requirements depend on the organization and systems.↩︎

20. NIST, Post-Quantum Cryptography FAQs, https://csrc.nist.gov/Projects/Post-Quantum-Cryptography/faqs. Distinguishes public-key risks and symmetric-cryptography considerations. Whether stored data needs rewriting depends on the deployed cryptographic design.↩︎

21. RISC-V International, “About RISC-V,” https://riscv.org/about/. Open instruction-set architecture; implementation and operating economics remain product-specific.↩︎

22. Amazon Web Services, “AWS Nitro System,” https://aws.amazon.com/ec2/nitro/. Describes offloading infrastructure functions from the main processors; no cross-generation performance result is inferred.↩︎

23. CXL Consortium, “About CXL,” https://computeexpresslink.org/about-cxl/. Coherent connectivity, memory expansion and pooling capabilities; deployed products support particular subsets and topologies.↩︎

24. Amazon Web Services, “AWS Graviton Processors,” https://aws.amazon.com/ec2/graviton/. Provider-designed Arm processors; product claims require workload validation.↩︎

25. Microsoft, “Azure Cobalt processor-based Virtual Machines,” https://learn.microsoft.com/en-us/azure/virtual-machines/sizes/cobalt-overview, checked October 3, 2026. Cobalt 100 architecture and physical-core-per-vCPU allocation; workload performance requires measurement.↩︎

26. Intel, “Intel Builds World’s Largest Neuromorphic System to Enable More Sustainable AI,” April 2024, https://www.intel.com/content/www/us/en/newsroom/news/intel-builds-worlds-largest-neuromorphic-system.html. Hala Point specifications and research purpose; energy comparisons need matched tasks and full-system boundaries.↩︎

27. University of Manchester, “SpiNNaker — Tomorrow’s computing today,” https://www.scieng.manchester.ac.uk/tomorrowlabs/spinnaker/; SpiNNaker2 architecture overview, https://arxiv.org/abs/2401.04491; TU Dresden, “Milestone for energy-efficient AI systems: TUD launches SpiNNcloud supercomputer,” April 2025, https://tu-dresden.de/tu-dresden/newsportal/news/milestone-for-energy-efficient-ai-systems-tud-launches-spinncloud-supercomputer, for the 35,000-chip system and the spin-off; SpiNNcloud, https://spinncloud.com/, checked October 3, 2026, for the eighteenfold GPU figure, a vendor claim.↩︎

28. BrainChip, “Akida Neuromorphic Processor,” https://brainchip.com/ip. Vendor description of a commercially licensed event-based processor; energy and accuracy claims require workload measurement.↩︎

29. SynSense, “Speck: Event-Driven Neuromorphic Vision SoC,” https://www.synsense.ai/products/speck-2. Vendor description of an integrated sensor-processor chip; vendor power claims apply to stated operating modes.↩︎

30. Innatera, “Pulsar,” https://www.innatera.com/product. Vendor description of a spiking microcontroller combining SNN, CNN and RISC-V elements.↩︎

31. Prophesee, “Metavision event-based sensors,” https://www.prophesee.ai/event-based-sensors. Vendor description of event-driven imaging; data-reduction ratios are workload-dependent.↩︎

32. Lightmatter, “Passage,” https://lightmatter.co/products/passage/. Vendor description of photonic interconnect; does not establish all-optical general computation.↩︎

33. Ayar Labs, “TeraPHY optical I/O chiplet,” https://ayarlabs.com/products. Vendor description of in-package optical interconnect; bandwidth, latency and power figures are vendor claims requiring system measurement. In 2026 the company reported its funding expanded to a $650 million total, https://ayarlabs.com/news/ayar-labs-expands-2026-funding-to-650-million/, and joined NVIDIA’s NVLink Fusion ecosystem for co-packaged optics, https://ayarlabs.com/news/ayar-labs-joins-nvidia-nvlink-fusion-ecosystem-to-bring-co-packaged-optics-to-rack-scale-ai-infrastructure/. Funding and ecosystem membership are not workload measurements.↩︎

34. Marvell, “Marvell Completes Acquisition of Celestial AI,” February 2, 2026, https://investor.marvell.com/news-events/press-releases/detail/1005/marvell-completes-acquisition-of-celestial-ai. Ownership of the Photonic Fabric technology; performance claims are vendor claims.↩︎

35. Lightelligence, https://www.lightelligence.ai/, checked October 3, 2026. Vendor descriptions of Photowave optical hardware for PCIe and CXL memory disaggregation and of its optical-computing boards.↩︎

36. Salience Labs, https://www.saliencelabs.ai/, and Tower Semiconductor manufacturing partnership, February 2026, https://towersemi.com/2026/02/25/02252026; Black Semiconductor, https://www.blacksemi.com/, checked October 3, 2026, for graphene photonics integrated on electronic chips, with a pilot fab under construction. Vendor descriptions of products in development. Salience Labs announced a $125 million Series B funding round on October 14, 2026, https://www.saliencelabs.ai/salience-labs-125-million-series-b-funding/, and demonstrated a 64-port all-optical circuit switch at the ECOC exhibition in September 2026, https://www.saliencelabs.ai/salience-labs-showcases-64-port-all-optical-circuit-switch-at-ecoc-2026/.↩︎

37. PR Newswire, “Volantis Raises $88M Series A to Demolish the AI Memory Wall With Photonics,” October 1, 2026, https://www.prnewswire.com/news-releases/volantis-raises-88m-series-a-to-demolish-the-ai-memory-wall-with-photonics-302895940.html; company site, https://volantissemi.ai/, checked October 19, 2026. Vendor descriptions: a photonic interconnect designed to connect compute chips to memory, built on micro-VCSEL light sources, with efficiency and capacity claims the company has not yet measured on a customer workload and first integrated inference engines planned for 2027.↩︎

38. NTT, NTT Innovative Devices, Japan Semiconductor, Furukawa Electric and Shinko Electric Industries, “Accelerating Development of Mass-Production Technologies for Photonics-Electronics Convergence Devices to Support Next-Generation AI Computing,” October 20, 2026, https://www.ntt-innovative-devices.com/en/news/2026/10/nedo.html. A four-company joint R&D proposal led by NTT Innovative Devices, with NTT as advisor, selected under NEDO’s Post-5G infrastructure and advanced-semiconductor manufacturing program to develop mass-production technologies for optical chiplets, targeting more than a tenfold increase in manufacturing productivity over research-stage processes and a pilot production line for future commercial manufacturing. A government-funded development program, not a product or a price.↩︎

39. Yichen Shen and colleagues, “Deep learning with coherent nanophotonic circuits,” Nature Photonics 11, 441–446, 2017, https://www.nature.com/articles/nphoton.2017.93. Experimental programmable photonic processor; the chapter makes no whole-system efficiency claim.↩︎

40. Q.ANT, “Native Processing Server,” https://qant.com/, and the company’s report of second-generation photonic processor deployments at the Leibniz Supercomputing Centre, March 17, 2026, https://qant.com/press-releases/higher-performance-less-energy-q-ant-deploys-second-generation-photonic-processors-at-supercomputing-center-lrz; DatacenterDynamics, March 18, 2026, https://www.datacenterdynamics.com/en/news/photonic-chip-company-qant-deploys-second-gen-photonic-processors-at-germanys-lrz/, for the 2018 TRUMPF spin-off. Vendor descriptions of a thin-film lithium-niobate photonic processor; efficiency claims are vendor claims and require end-to-end comparison.↩︎

41. Sufi R. Ahmed and colleagues (Lightmatter), “Universal photonic artificial intelligence acceleration,” Nature 640, 368–374, April 9, 2025, https://www.nature.com/articles/s41586-025-08854-x. Supplementary Information, Table S4 and text: 262 TOPS/W for the tensor core’s encoding energy alone; 0.81 TOPS/W average and 1.75 at peak for the complete processor, against 0.42 to 1.41 for five NVIDIA GPUs. The ratio 262 ÷ 0.81 ≈ 323 is calculated here.↩︎

42. Mythic, “How it Works,” https://www.mythic.ai/technology/, and “Vanguard,” https://www.mythic.ai/vanguard, checked October 3, 2026, for its flash-based analog die with 4,096 converters and digital control die. Vendor claims; efficiency and quality must be evaluated on the intended workload.↩︎

43. Weebit Nano, “Weebit Nano expands licensing agreements with key customers; three customer chip designs taped-out to-date,” July 31, 2026, https://www.weebit-nano.com/news/press-releases/weebit-nano-expands-licensing-agreements-with-key-customers-three-customer-chip-designs-taped-out-to-date/, and “Weebit Nano reports on 2025 targets achievement,” January 2026, https://www.weebit-nano.com/news/press-releases/weebit-nano-reports-on-2025-targets-achievement/. Company announcements of tape-outs, the qualification estimate, DB HiTek qualification and licensees. Weebit’s ReRAM was also fully qualified for SkyWater Technology’s 130 nm S130 process in June 2023, https://www.weebit-nano.com/news/press-releases/weebit-nanos-reram-ip-now-fully-qualified-in-skywater-technologys-s130-process/. In November 2026 Weebit launched the Matrix In-Memory Compute Research Program, supplying qualified researchers with an evaluation or quick-start package built on a 32 × 32 crossbar array designed for multiply-accumulate and spiking-network experiments, https://www.weebit-nano.com/news/press-releases/weebit-nano-launches-weebit-matrix-in-memory-compute-research-program/ — a research kit, not a product; the release relays one evaluator’s projection of roughly eighty-fold lower power than a GPU implementation for an inference workload, a vendor-relayed claim, not a published measurement.↩︎

44. Weebit Nano, “Weebit Nano expands licensing agreements with key customers; three customer chip designs taped-out to-date,” July 31, 2026, https://www.weebit-nano.com/news/press-releases/weebit-nano-expands-licensing-agreements-with-key-customers-three-customer-chip-designs-taped-out-to-date/, and “Weebit Nano reports on 2025 targets achievement,” January 2026, https://www.weebit-nano.com/news/press-releases/weebit-nano-reports-on-2025-targets-achievement/. Company announcements of tape-outs, the qualification estimate, DB HiTek qualification and licensees. Weebit’s ReRAM was also fully qualified for SkyWater Technology’s 130 nm S130 process in June 2023, https://www.weebit-nano.com/news/press-releases/weebit-nanos-reram-ip-now-fully-qualified-in-skywater-technologys-s130-process/. In November 2026 Weebit launched the Matrix In-Memory Compute Research Program, supplying qualified researchers with an evaluation or quick-start package built on a 32 × 32 crossbar array designed for multiply-accumulate and spiking-network experiments, https://www.weebit-nano.com/news/press-releases/weebit-nano-launches-weebit-matrix-in-memory-compute-research-program/ — a research kit, not a product; the release relays one evaluator’s projection of roughly eighty-fold lower power than a GPU implementation for an inference workload, a vendor-relayed claim, not a published measurement.↩︎

45. Normal Computing, “Normal Computing Announces Tape-Out of World’s First Thermodynamic Computing Chip,” August 12, 2025, https://www.normalcomputing.com/blog/normal-computing-announces-tape-out-of-worlds-first-thermodynamic-computing-chip, including the CN201 and CN301 roadmap; experimental system in Nature Communications, https://www.nature.com/articles/s41467-025-59011-x. A tape-out is a fabrication milestone, not a product; the claim to be first and the efficiency targets are vendor claims.↩︎

46. Extropic, “Extropic Signs $75 Million Letter of Intent with U.S. Department of Commerce to Scale and Onshore Thermodynamic Computing,” July 29, 2026, https://extropic.ai/writing/thermodynamic-computing-chips-in-america. The release states that the letter is non-binding and that funding depends on definitive agreements and milestones. Performance claims are vendor claims.↩︎

47. Extropic, “Hardware,” https://extropic.ai/hardware, checked October 19, 2026. Vendor descriptions: X0, a silicon prototype (first quarter 2025), and XTR-0, an experimental research platform (third quarter 2025); Z1 Stick, an M.2 module carrying over half a million probabilistic bits, and Z1 Card, a PCIe card carrying over four million, both listed as early access 2027. Product status is the company’s own account; no workload measurements are published.↩︎

48. Dina Genkina, “Reversible Computing Escapes the Lab,” IEEE Spectrum, January 2, 2025, updated May 22, 2025, https://spectrum.ieee.org/reversible-computing. Landauer’s limit, adiabatic switching and resonant recovery; CMOS uses more than a thousand times the minimum energy per erased bit.↩︎

49. EE Times, “Vaire Demos Energy Recovery With Reversible Computing Test Chip,” 2025, corrected September 4, 2025, https://www.eetimes.com/vaire-demos-energy-recovery-with-reversible-computing-test-chip/, reporting recovery factors of 1.77 (capacitor array) and 1.41 (shift register) against square-wave drive; Science News, September 23, 2025, https://www.sciencenews.org/article/computer-chip-reuses-energy; Vaire Computing, https://vaire.co/. Test structures, not a product benchmark.↩︎

50. D-Wave, “The Leap Quantum Cloud Service,” https://www.dwavequantum.com/solutions-and-products/cloud-platform; SLA announcement, October 3, 2024, https://www.dwavequantum.com/company/newsroom/press-release/d-wave-introduces-service-level-agreements-for-leap-quantum-cloud-customers-in-production; AWS Marketplace listing, https://aws.amazon.com/marketplace/pp/prodview-swm25ss53l2ss, checked October 26, 2026, where private offers are also available. The availability figure is the vendor’s monitoring data; the announcement does not publish the SLA’s terms.↩︎

51. D-Wave, “D-Wave Launches Gate-Model Simulator Beta Program, Advancing Error-Aware Programming Capabilities,” October 1, 2026, https://www.dwavequantum.com/company/newsroom/press-release/d-wave-launches-gate-model-simulator-beta-program-advancing-error-aware-programming-capabilities. Vendor announcement of a simulator beta accessed through Leap and the Ocean SDK; names BBVA, FirstQFM, Florida Atlantic University and the Jülich Supercomputing Centre as beta participants, and cites peer-reviewed validation of the dual-rail architecture’s two-qubit entangling gate in Nature. The dual-platform framing and the error-correction efficiency claims are vendor claims; the gate-model systems are forward-looking.↩︎

52. D-Wave and SkyWater, “SkyWater and D-Wave Extend Quantum Manufacturing Collaboration Through Multi-Year Agreement,” October 13, 2026, https://www.dwavequantum.com/company/newsroom/press-release/skywater-and-d-wave-extend-quantum-manufacturing-collaboration-through-multi-year-agreement: a multi-year extension of a Minnesota-fab relationship spanning more than a decade, including fabrication of Advantage2 processors. IonQ announced an agreement to buy SkyWater in January 2026, https://www.wsj.com/business/deals/quantum-computing-company-ionq-to-buy-chip-maker-skywater-for-1-8-billion-08916998, and its October 2026 announcements describe SkyWater as part of IonQ’s chip design, fabrication and packaging capabilities, https://www.ionq.com/news/ionq-to-acquire-elisity-to-accelerate-zero-trust-for-the-quantum-era; it also completed the acquisition of photonics manufacturer Nexus Photonics in September 2026, https://ionq.com/news/ionq-completes-acquisition-of-nexus-photonics-securing-scalable-manufacturing-for-quantum-systems, and announced the acquisition of cybersecurity firm Elisity the same month. Company announcements; both D-Wave and SkyWater describe the manufacturing collaboration as continuing.↩︎

53. ASML, “TWINSCAN NXT:1965Ci,” https://www.asml.com/en/products/duv-lithography-systems/twinscan-nxt-1965ci. Documents a 26 × 33 mm full exposure field; field size varies with lithography system.↩︎

54. Gene Amdahl, oral history interview by William Aspray, Computer History Museum, September 24, 2000, https://archive.computerhistory.org/resources/access/text/2013/05/102702492-05-01-acc.pdf, pp. 34–35, for the leakage, mask turnarounds, Elxsi purchase and CMOS remark; “Trilogy Systems,” https://en.wikipedia.org/wiki/Trilogy_Systems, for the founding, the funding record and the mid-1984 decision to abandon the design.↩︎

55. Cerebras, wafer-scale chip and systems description, https://www.cerebras.ai/chip, and inference service, https://www.cerebras.ai/inference. Commercial vendor descriptions; no universal performance or economic advantage is inferred.↩︎

56. Cerebras, “Cerebras Unveils CS-4: Up to 30 Times Faster than GPU-based Solutions,” August 18, 2026, https://investors.cerebras.ai/news-releases/news-release-details/cerebras-unveils-cs-4-30-times-faster-gpu-based-solutions. Vendor announcement of a rack-scale system built from three Wafer-Scale Engine 3 Turbo processors; the speed and throughput-per-watt comparisons are vendor benchmarking claims requiring workload measurement. The CS-3 facility figures quoted in the text describe the prior-generation datasheet.↩︎

57. OpenAI, “OpenAI partners with Cerebras,” January 14, 2026, https://openai.com/index/cerebras-partnership, announcing 750 megawatts of Cerebras systems for OpenAI’s platform in tranches through 2028; CNBC reported the arrangement as worth more than $10 billion, attributing the figure to people close to the companies, https://www.cnbc.com/2026/01/14/cerebras-scores-openai-deal-worth-over-10-billion.html. Cerebras, “Cerebras Powers Ultrafast Mode for OpenAI’s GPT-5.6 Sol,” August 13, 2026, https://investors.cerebras.ai/news-releases/news-release-details/cerebras-powers-ultrafast-mode-openais-gpt-56-sol, describing a limited-preview service tier running at a claimed 750 output tokens per second. Partner and vendor announcements: the deployment schedule and performance figures are the parties’ claims, to be re-verified as tranches and tiers reach general availability.↩︎

58. Cerebras, wafer-scale chip and systems description, https://www.cerebras.ai/chip, and inference service, https://www.cerebras.ai/inference. Commercial vendor descriptions; no universal performance or economic advantage is inferred.↩︎

59. Cerebras, Wafer-Scale Cluster datasheet (CS-3 system), https://www.cerebras.ai/product-cluster, checked October 3, 2026. Per node, a CS-3 listed with supporting servers and switches: 42U rack, 800 kg, 34 kW provisioned, facility water or liquid-to-air cooling. Cerebras described the CS-3 alone as 15U and up to 23 kW in 2024, https://www.cerebras.ai/blog/cerebras-cs-3-vs-nvidia-b200-2024-ai-accelerators-compared, and lists it at 16U today, https://www.cerebras.ai/cs3; confirm the purchased configuration’s requirements.↩︎

60. Vendor and project pages are each organization’s own description of its products; links checked November 9, 2026. A link locates the evidence this chapter asks for; it is not an endorsement or an independent verification of the claims on the page.↩︎